Boss - DD-3 Digital Delay  [schematic]

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Bernardduur
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Post by Bernardduur »

Nice page on all the versions

So, I got this DD3 in that I could not recognise from the insides. I have seen a lot of different versions over the years (Big IC, IC on the 'other' side of the board, SMD units, etc) but this one is different.

I got this in for a trails mod, a mod I've done a lot on the older models. But this unit lacks the common points I use to perform the mod. There is no 570 IC in this unit and the signal path is different. It also sounds not like my own DD3...... more clean-ish and the repeats don't drown that nice with the feedback cranked.....
I call it version 4
Boss - DD3 v4 1.JPG
Boss - DD3 v4 2.jpg
Boss - DD3 v4 3.jpg
DD3 v4.JPG
'No more....... loud music.......'
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Post by Bernardduur »

Service notes for the 1st and 3rd version
DD-3A_SERVICE_NOTES.pdf
(941.04 KiB) Downloaded 539 times
DD-3T_SERVICE_NOTES[1].pdf
(1.01 MiB) Downloaded 319 times
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Post by floris »

A question about the Boss DD3-A:
DD-3A_SERVICE_NOTES.pdf
https://www.freestompboxes.org/download/ ... p?id=27741

Mine has only clean signal but no delay signal.

I see that the AD conversion is done by a "Successive approximation ADC" with the micro-controller IC7, the resistor ladder RA1, Sample&Hold circuit with 4066 IC3c with cap C017, and comparator IC5.
Because of the "Successive approximation ADC", I see that output of the resistor ladder RA1 and buffer opamp IC8b, is fed back into the comparator IC5 pin 2, as expected. So I expect this to be the approximated input signal.

I'm confused about the delayed signal output, coming from the micro controller IC7.
It looks like this also comes from resistor ladder RA1 and opamp output IC8b, and then goes to Sample&Hold circuit 4066 IC3b with cap C033, and from there to Q006.

Is it so that the DA output of the resistor ladder and opamp 8b, is switched between the "delayed signal" and the "approximated input signal"?
And that the S&H circuit of IC3b makes sure that only the "delayed signal" goes to Q006?

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Post by Dirk_Hendrik »

I'd say your analysis is correct.
Sorry. Plain out of planes.

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Post by microbailey »

floris wrote:A question about the Boss DD3-A:
DD-3A_SERVICE_NOTES.pdf
https://www.freestompboxes.org/download/ ... p?id=27741

Mine has only clean signal but no delay signal.

I see that the AD conversion is done by a "Successive approximation ADC" with the micro-controller IC7, the resistor ladder RA1, Sample&Hold circuit with 4066 IC3c with cap C017, and comparator IC5.
Because of the "Successive approximation ADC", I see that output of the resistor ladder RA1 and buffer opamp IC8b, is fed back into the comparator IC5 pin 2, as expected. So I expect this to be the approximated input signal.

I'm confused about the delayed signal output, coming from the micro controller IC7.
It looks like this also comes from resistor ladder RA1 and opamp output IC8b, and then goes to Sample&Hold circuit 4066 IC3b with cap C033, and from there to Q006.

Is it so that the DA output of the resistor ladder and opamp 8b, is switched between the "delayed signal" and the "approximated input signal"?
And that the S&H circuit of IC3b makes sure that only the "delayed signal" goes to Q006?
Yes. The DAC (which is formed form RA1 + 8b) is doing both the functions. It will work like this, in time order:
1. IC7 pin 28 pulses (once very audio sample) and will sample the audio input waveform voltage on C017, and the delayed output audio waveform voltage on C033. This will be a narrow pulse.
2. IC5 compares the sampled input voltage to the voltage on 8b pin 7 and the ADC conversion starts working. IC5 pin 7 is binary (either low or high voltage) feeding a string of fast pulses into IC7 pin 30
3. Over the next 12 pulses (probably the clock on pin 84) IC7 will update the binary values driving RA-1 and respond to the high/low on pin 30 (the binary values on pin 30 are "shifted" into IC7 pin 30 on each clock pulse)
4. When the A-to-D conversion is finished (all 12 bits are done) and held inside IC7, IC7 switches to outputing the delayed digital sample value (which it has retrieved from IC6) on RA-1 and so 8b now has the delayed signal waveform voltage
5. IC7 pin 28 pulses again and this delay sample is 'pushed' onto C033. Simultaneously the input signal is sampled again (see #1) above and the loop starts over again

So in summary, 8b pin 7 is providing both the delayed sample (on C033) and playing its part in the successive approximation ADC conversion of the analog value on C017. It swicthes between these functions very quickly.

I hope that all makes sense :scratch:

You should be able to measure (if you have a scope) the voltage on C033 or better on Q006 source and see your delayed audio as a waveform.
If nothing there, try 8b output - this will be jumping around but at least you should see it change when there's audio coming in.
If that's all dead check the basics - is there a square wave clock on IC7 pin 84, are RAS and CAS lines on IC6 toggling?

If you don't have a scope it'll be tough fault finding a digital circuit like this.

Hope that helps a bit :D
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Post by floris »

Thanks for the detailed explanation, it confirms what I was thinking and makes it all very clear.
Yes I have a scope, so I'll probe some more to see what is failing. Currently I suspect the Sample & Hold circuit IC3b 4066.

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Post by microbailey »

floris wrote:Thanks for the detailed explanation, it confirms what I was thinking and makes it all very clear.
Yes I have a scope, so I'll probe some more to see what is failing. Currently I suspect the Sample & Hold circuit IC3b 4066.
Good luck. Those 4066 chips can get easily blown by static discharge if I remember well so could be damaged.
Look for dry joint on the board too - many old boards have dry joints which are PITA to find :x
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Post by floris »

microbailey wrote: You should be able to measure (if you have a scope) the voltage on C033 or better on Q006 source and see your delayed audio as a waveform.
If nothing there, try 8b output - this will be jumping around but at least you should see it change when there's audio coming in.
If that's all dead check the basics - is there a square wave clock on IC7 pin 84, are RAS and CAS lines on IC6 toggling?
I did some measurements with my scope and a sine signal as input:
- Sampling of the input sine wave is working, I see a nice "staircase" signal of the sine input wave on IC3c pin 8, so IC3c and IC5 and the sample&hold pulse out of the CPU IC7 (IC7 pin 28, and IC3c pin 6) are all working.
- Sample&Hold pulse out of the CPU IC7 reacts to the Delay Time setting, so that is working.
- I do see the successive approximation taking place on IC3b pin 3. I can make out the correct sine wave value that it approximated. So CPU IC7 and IC8 are working.
- There is no (delayed) signal on Q006 nor on C033, nor on IC3b pin 4. When I looked at the scope, probing the S&H pulse out of the CPU on IC3b pin 5 and probing the signal out of the CPU on IC3b pin 3, I see that:
When the S&H pulse occurs, there is no signal out of the CPU. So the successive approximation of the sine input wave does take place, that part works, but there seems to be no delayed signal coming from the CPU.
- I do see the RAS and CAS lines on IC6 (memory chip) toggling. Also I see activity on the various data and address lines of IC6.

Only thing I can think of at the moment, is that the memory chip IC6 is not working somehow, because the delayed signal is not coming out of the CPU even though the input signal is approximated and is AD converted by the CPU.

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Post by microbailey »

Sounds like most of this circuit is alive and well, so I'm thinking the fault is more basic.
Are IC7 pins 25, 59, 63, 65, 23, and 26 all as expected (the levels coming from the pedal switches)? if those signals are not right or are floating (say due to a broken switch or a bad solder joint/PCB trace) then the program in IC7 may think the delay is disabled and mute the delayed readback output.

Also if you have 2 channels on your scope. trigger off the OE pin on IC6 (pin 5) and with your other channel check that when OE pin goes low (= close to 0V) that D1 to D4 out of IC6 are driving some 1s and 0s data out (not all 0s). This would be your delayed data coming back out of RAM, so you'll need your sinewave connected to get data into the RAM in the first place.
You probably already know this, but when IC6 OE is high (and WE low) the audio data is being written to the RAM, and when OE is low (and WE is high) the audio data is being read back from the RAM to give the impression of a delay.

Sounds like you're close to cracking this one.

Btw - good rule is always look for the simplest cause of fault (bad connections) and then look for broken components.
The time to reverse that rule is when there something on the PCB which is on fire :shock:
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Post by floris »

Thanks again for thinking about this with me. Much appreciated. :thumbsup
I will try your suggestions and see where that takes me.
Learning something new every day! :-)

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Post by Dirk_Hendrik »

I forgot...
replace all 10uF caps. I guess that's the most common repair I have done on many (many!!) dead DD3's.
Sorry. Plain out of planes.

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Post by floris »

Thanks for the tip Dirk.
I have repaired a few DD3s by replacing the bad 10uF caps. In those cases I could always measure that some coupling capacitor did not pass the signal. This seems not to be the case with this one.

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Post by floris »

IC7 pins 23 EFSW, 25 FETSW and 26 HOLD, seem to work as they should. The LED also works as it should.

But I'm having difficulty with interpreting the states of pins 59 MUTE, 63 TIME4, 65 TIME6. They work with the Mode of the pedal.
The Mode knob connects:
- MUTE with TIME4 in 50ms Mode.
- MUTE with TIME6 in 200ms Mode.

Measurements:
- IC7 pin 59 MUTE: 0V 800ms, 0V 200ms, 0V 50ms, 0V Hold pressed & not pressed.
- IC7 pin 63 TIME4: 5V 800ms, 5V 200ms, 0V 50ms, 5V Hold pressed & not pressed.
- IC7 pin 65 TIME6: 5V 800ms, 0V 200ms, 5V 50ms, 5V Hold pressed & not pressed.

MUTE is always 0V regardless of Mode or pressing the foot-switch. This does not seem good to me.

Does anybody know how the MUTE and TIME4 TIME6 lines of IC7 are supposed to work?
Which are inputs and which are outputs?

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Post by floris »

Seeing that MUTE (IC7 pin 59) is connected to the inputs of IC4d and IC4b via the Mode switch in Hold position, I can probably assume that MUTE is an output?
So why is MUTE always at 0V in my DD3 version A?

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