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I couldn't find any vero layouts on the interwebs for R.G. Keen's JFET matcher, so i went ahead and made one. I didn't have any single op-amps, so i made a layout that uses half of a dual op-amp.

Problem is, it's not working, and i've been going over the layout like crazy for the last hour. I just can't see what i've done wrong.
Everytime i stick a JFET in there, the DMM readuot drops from V+ to Vmid (9.44V - 4.87V). I find it kind of hard to believe that all of my 2N5457's have a vgs of 4.87V

Do any of you guys see some mistakes here?

My first impression is that your layout looks good. With your DMM probe at pin 3 you should never read more than 1/2 V+
or 4.5V (4.7V with a 9.4V supply) no matter where you touched the other probe. If the 10k/10k voltage divider was not
grounded properly then that capacitor would charge up to 9V (9.4V in you case) and you could get 9V readings like you
apparently are. Power it up....place your negative probe on 0V and the positive probe on pin 3 and measure. If you read
4.5V (4.7V) then that part is fine. But, if it reads higher there's a problem. I suspect a simple problem like a solder bridge,
cold solder joint, or a trace cut that didn't quite completely sever the trace. If all else fails you can try grounding the unused
pins of the op amp.

The unused half of the opamp could be oscillating and upsetting things, it has both inputs open circuit.

Try setting it as a unity gain buffer, -ve input to output, and connect the +ve input to the the used +ve input (pseudo 0v)

Tsk! I had a jumper wrong in my build. The circuit works now, and my layout is verified Thanks for the help guys!

But it's true what deltafred said: Never leave an unused opamp unconnected.
Connect it as shown here for "IC1b":
http://forum.musikding.de/cpg/albums/us ... c_v1-2.jpg
Pin 5 could go to gnd instead.