I've been working with similar SMD JFETs lately and I really like this setup.soulsonic wrote:My Shizzle Deluxe Fuzz/Overdrive uses this technique for the JFET input stage. In this case, the bias isn't adjustable, because it consistently gives the right biasing with these values with this transistor...stole59 wrote:Wow man, I never saw anything like this in Jfet pedal design.
You will also see this in some of the Russian-designed JFET circuits.
Trying to deconstruct:
Looks like you set the ID at 60% of the specified IDSS minimum for the Y variant.
Source resistor is about 25% of total D-S resistance.
Then, you select the gate voltage divider resistor value based on a target drain voltage?
I've had good results this way, but my sample size is still pretty small, using JFETs from the same reel.