Hi!
unfortunately we didn't bring our headphones today, we will listen to your sample later when we have access to them
!
About the linearization resistor: We didn't pay attention, it's our fault, sorry! The stage is AC coupled, so that the additional resistor shifts the bias of C1, the signal dropout should come from the signal drifting out of range of the successive stages, which causes the signal to disappear. Uhm - we'll need to think a minute about how to resolve that properly, and we need to get some paid work done today first, will come back to you about that
! But yeah, in theory it should be equal to the gate resistor and apply 1/2 of the input signal to the gate. If you're interested in the details, you can check out the section "FETs as variable resistors" in The Art of Electronics, you should be able to find an old edition as a free pdf online easily if libraries are currently closed in your area - long story short, it compensates for the square law of FETs in the low voltage region. This is however quite a soft clipping, we suspect that it doesn't help much with the distortion you have issues with.
About distortion: Since you use the common emitter amplifiers with a different gain than originally, they are now probably misbiased. In your circuit, Q4-Q7 all are common emitter amps (Q2 and Q3 are a discrete darlington buffer, they should be fine as they are). Let's go through how they work quickly so you can understand how to fix it (all from the perspective of NPNs):
- Base and emitter form a diode, as is hinted in the circuit symbol. The input signal is applied at the base, and as long as some forward current flows through this diode, the emitter signal is pretty much identical to the base, except for the typical diode voltage drop of 0.6-0.7V for silicon. In case of Q4, R17 guarantees that saturation as long as the base is more than a diode drop above ground.
- In a first approximation, the current flowing into the base is mirrored to the collector, multiplied by a transistor parameter called beta or hfe, which is typically around 100-1000 for standard transistors. If we don't look too closely, we can therefore say that the emitter current is basically identical to the collector current, and the base current is a small fraction of that. If we'd tie the collector directly to +9V, this would form a simple buffer, a so-called emitter follower; it's a buffer since the emitter voltage follows the base voltage, but almost all the current that following stages might draw from the emitter output is supplied by the collector, and the base signal is only marginally loaded. This works as long as the collector is at a higher voltage than the emitter, above that clipping occurs. Actually, there's some soft clipping before that, but we'll ignore that for now.
- As you can see, for Q4 the collector isn't tied directly to +9V, but there's R18 in the way - since we neglect base current, all the current flowing through the emitter resistor also flows through the collector resistor! This means if the collector resistor is twice the emitter resistor, there's twice the voltage across it - we built an amplifier, and gain simply -R18/R17. The minus sign comes from the fact that the emitter resistor's more negative side is tied to a voltage source, whereas it's the opposite for the collector resistor. This is just a simple first approximation, there's a bunch of side effects that should be taken into account for exact calculation, but for a rule of thumb it's good enough.
- Since the collector must be at higher voltage than the emitter, the original signal and the amplifier have to "share" the same headroom: This means for an amplifier with a gain of -2 for example you might want the emitter to swing between 0 and 3 volts and the collector between 3 and 9 volts, so that the available supply voltage is used optimally. Therefore we'd like the emitter to be biased at around 1.5V, and do that by biasing the base to around 2.2V. Often the bias voltage divider is connected to ground at one end, but on the other end it's hooked up to the collector instead of +9V - this is done to make the actual output bias a bit less dependent on the temperature dependent diode drop, and is often called autobias. It also decreases gain since it introduces negative feedback, but we won't worry about that here.
You could go ahead and calculate the values, but since you've already got the circuit on breadboard you can just measure: The collector voltages should be:
Q4: 6.7V
Q5: 5V
Q6: 7.5V
This needn't be precise, if you're within +-0.3V that's perfectly fine. We'd recommend adjusting the collector-base resistors R15, R19 and R23 to get to the desired value. Also, since Q6 is at lower gain than Q5, it actually restricts the headroom of the circuit. You might also consider running Q4 with less idle current and replace both R17 and R18 by maybe 1k or 2.2k resistors, whichever you have at hand.
We're not sure how willing you are to change the circuit topology, but if it was us we'd grab the signal for Q6 from Q4 instead of Q5, increase the gain of Q6 and put a volume pot in between - this way, the noise from Q6 will always be present regardless of output volume, but Q5 is the first stage that would clip and this way it would only affect the side chain. Q6 could have the same configuration as Q5, but since there's a volume pot before it it would be possible to reduce its input gain.
Wow this got way longer than expected. Sorry for rambling. Will listen to your sample later and come back about linearizing the FET!
