Weird issue with high voltage mosfet buffer  [SOLVED]

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Reachahighernoon
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Post by Reachahighernoon »

So recently I made a tube preamp that utilizes an output buffer similar to that one found on the Meatsmoke preamp. It is powered by the typical 555 timer based SMPS delivering 180 volt to the plate and 12 volts to the heaters

The issue is as follows: Upon powering up and after the preamp warmed up the sound would be gated and had a very low volume, the distortion sounded like a very gated fuzz and the clean had a weirder quality to it: The clean sound had a very low volume until you struck the strings very hard and the preamp produced, again, a loud gated fuzz type of sound. The mosfet used was an IRF740, I then replaced it with an IRF840 but the issue persisted

I attributed this to the mosfet because once I accidently touched the body of the mosfet(the drain) to the 12V power supply line sparks flew and suddenly the preamp started sounding properly on both clean and distorted settings

I since then removed the mosfet and replaced it with a typical jfet buffer powered directly by the 12V power supply and the issue was gone

Has anyone encountered such an issue or has any clue as to what the issue can be? Below is the schematic of said buffer
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stolen
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Post by stolen »

Hi!

No wonder it's gating, the input bias is essentially completely floating! The FET gate needs to be tied to some reference voltage, preferably via a large (~1-10M) resistor, else the voltage across C26 drifts to whatever it feels like, D5 does little to help. The "B" node is 180V, right? In that case biasing to B/2 with a voltage divider is fine. For maximum headroom you might wanna make that trimmable to account for the variations in FET manufacturing, but it is probably not significant and this supply voltage.

If noise isn't critical, a divider of 2 metal film 10M resistors to the gate should be fine, else you might wanna bypass a divider with a large cap and tie that to the gate with a third resistor to avoid flicker noise from the comparably large DC.

Hope this helps,
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Post by Reachahighernoon »

stolen wrote: 20 Sep 2021, 11:44 Hi!

No wonder it's gating, the input bias is essentially completely floating! The FET gate needs to be tied to some reference voltage, preferably via a large (~1-10M) resistor, else the voltage across C26 drifts to whatever it feels like, D5 does little to help. The "B" node is 180V, right? In that case biasing to B/2 with a voltage divider is fine. For maximum headroom you might wanna make that trimmable to account for the variations in FET manufacturing, but it is probably not significant and this supply voltage.

If noise isn't critical, a divider of 2 metal film 10M resistors to the gate should be fine, else you might wanna bypass a divider with a large cap and tie that to the gate with a third resistor to avoid flicker noise from the comparably large DC.

Hope this helps,
stolen
Holy hell I'm a freaking idiot! The first thing I thought to myself was "hurr durr but the meatsmoke preamp output buffer isnt biased!" Yes it freaking is!

Image

And then I looked at another schematic for a similar output buffer and same damn thing, except this time it is referenced to ground via 1M resistor!

Scratch that, it isnt biased to ground, it's biased to ground through another 47K resistor. THANK YOU!
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Post by Reachahighernoon »

Then there's this example: I thought that Rp is simply a plate load resistor for V1, but it also serves as gate bias for the mosfet no?

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Reachahighernoon wrote: 20 Sep 2021, 11:59 Then there's this example: I thought that Rp is simply a plate load resistor for V1, but it also serves as gate bias for the mosfet no?

Image
Yeah, there simply is no DC blocking here and remains defined in-between stages. A simple way to think about this is just eliminate all capacitors from a circuit (in your mind, not irl) and see if all nodes still are well-defined. One gets used to it. One of those has sort of a positively bootstrapped bias, which doesn't look like the best idea, but whatever works?

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Post by Reachahighernoon »

stolen wrote: 20 Sep 2021, 13:16
Reachahighernoon wrote: 20 Sep 2021, 11:59 Then there's this example: I thought that Rp is simply a plate load resistor for V1, but it also serves as gate bias for the mosfet no?

Image
Yeah, there simply is no DC blocking here and remains defined in-between stages. A simple way to think about this is just eliminate all capacitors from a circuit (in your mind, not irl) and see if all nodes still are well-defined. One gets used to it. One of those has sort of a positively bootstrapped bias, which doesn't look like the best idea, but whatever works?
Yeah from what I understand it is usually better for all stages to be coupled via capacitors....why I dont know though...

And what do you mean by positively bootstrapped bias?

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Reachahighernoon wrote: 20 Sep 2021, 11:57 Scratch that, it isnt biased to ground, it's biased to ground through another 47K resistor. THANK YOU!
This one's positive feedback bias. It's kinda cursed; there's a technique called autobias (a negative feedback technique) which is intended to reduce sensitivity to variance by temperature drifts or FET manufacturing etc., this one here is kinda the opposite and actually amplifies these issues in order to keep component count as low as possible. We wouldn't recommend it.

As for DC blocking (capacitor coupled) biasing: Many amplifier topologies used in audio are not particularily precise in the DC domain; this means if we assume a linear transfer curve and say output = gain * input + offset, we often don't know (or care) what the offset across temperature ranges and component instances is; if you plug a couple of IRF830 into your circuit and measure output voltage, you'll see differences, and that's typically not a problem since we only care how the signal swings, not where.

It however does become a problem when you apply significant gain: Say we have a typical guitar pedal, supplied with 9V so that each stage can only swing between 0V and 9V, typically less, and we use a gain of say 1000: Without any input signal, we might want the output of the gain stage to sit at something like 4.5V so it can swing far in either direction. Consider that the signal comes from some previous stage that isn't particularly precise, so that the input is 0.01V away from where it should be; this means the output is 1000 times as far away, or at theoretically 14.5V! It can't possibly reach that value, so it sits somewhere below, and small input signals will be ignored entirely, effectively gating the signal. This can of course be desirable, and such misbiased circuits can sound great, but it can be a problem, especially if 5 degrees temperature shift turn your heavy overdrive into a gated fuzz.

Enter the capacitor magic: An ideal cap is completely ignorant of the voltage across it. In the configurations above it's a high pass*, which makes use of that property in that it doesn't care what the bias of the previous stage is and instead shifts the signal to whatever the DC bias of the following stage is. We'll skip how to determine that bias generally, it's a bit too involved for this post when feedback is involved, but in the simplest case where the resistor is tied to a constant voltage and the input of the stage doesn't draw significant current (such as a FET gate) it's simply that constant voltage. This means we have removed any influence that bias shifts of the previous stages might have!

Using feedback, this technique can also be applied to make up for variations in the amplifying stage itself by making a little circuit that looks at the output bias and shifts the input bias accordingly. This is sometimes called autobias and is well demonstrated in simple transistor amplifier circuits such as the Big Muff or Box Of Rock, but a humble inverting OPA amplifier uses the same technique as well. In these circuits, this bias feedback affects signal frequencies too and thus reduces gain, but that can be bypassed if desired.

All of this hardly matters if the gain of a circuit is very low, and a buffer with a gain of 1 certainly doesn't care much; however it might require a different bias than the preceding stage provides, in which case rebiasing the signal with a capacitor is often the simplest solution. If however their ranges match up nicely, directly tying them together is perfectly fine and is actually very common.

A little extra on how the high pass rebiasing actually works: You may be familiar with the simple RC lowpass/highpass circuits. When people mention them, they often miss out a crucial detail: Both of them are the same circuit, and it's a crossover mixer, taking the low frequencies from the resistor side and the high frequencies from the capacitor side. Now, DC is a zero Hertz wave, the lowest possible frequency, so any DC on the capacitor side is fully ignored :D! And yes, you can use this simple circuit as an actual audio crossover mixer, which is very useful sometimes. You might be tempted to set the corner frequency very very low to not make the high pass cut any bass, but this also increases chargeup time, so 1-10Hz is usually a good value.

The bias point is where no current flows into the capacitor, hence for DC analysis we can just imagine them to be gone. However, when the circuit powers up the cap needs to be charged up to that voltage, and there's unfortunate (positive feedback/negative resistance) configurations where the cap doesn't drift towards bias, but away from it; with simple circuits such as above you're unlikely to run into that issue, but it's useful to keep in mind. Your case is right in-between; since nothing except for the diode can really sink/source current into the cap to charge it into its proper operating region, it just sits wherever it wants to.

Hope this helps!
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*this is not a general property of high passes, other topologies may transfer DC.

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Post by Reachahighernoon »

Wow that's a lot of info

So what you're saying about the biasing of the gate is that it's better to use a reference from the drain of the mosfet(or plate of the tube)? This is called negative feedback bias, right?

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Post by Reachahighernoon »

stolen wrote: 20 Sep 2021, 13:16
Reachahighernoon wrote: 20 Sep 2021, 11:59 Then there's this example: I thought that Rp is simply a plate load resistor for V1, but it also serves as gate bias for the mosfet no?

Image
Yeah, there simply is no DC blocking here and remains defined in-between stages. A simple way to think about this is just eliminate all capacitors from a circuit (in your mind, not irl) and see if all nodes still are well-defined. One gets used to it. One of those has sort of a positively bootstrapped bias, which doesn't look like the best idea, but whatever works?
OK so I tried a 330K from Drain to R29 and that didnt work, it just produced a lot of white noise, then I tried 1M from the anode of the diode to R29 and it still sounded gated

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Post by stolen »

Wait which circuit are we talking about now? The one from the first post? Try the voltage divider we suggested. 10M from B+ to gate and another 10M from gate to ground. If it doesn't work, measure the voltage at the source in this configuration and adjust the divider until it is very roughly at about B+/2.

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Reachahighernoon wrote: 20 Sep 2021, 16:41 Wow that's a lot of info

So what you're saying about the biasing of the gate is that it's better to use a reference from the drain of the mosfet(or plate of the tube)? This is called negative feedback bias, right?
If there's any significant signal at the drain, yes. That's not the case in the buffer configuration though. Also it still needs to be shifted in most cases - note that those resistors usually form only one half of a divider, unless it's an OPA.

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Post by Reachahighernoon »

stolen wrote: 20 Sep 2021, 21:25 Wait which circuit are we talking about now? The one from the first post? Try the voltage divider we suggested. 10M from B+ to gate and another 10M from gate to ground. If it doesn't work, measure the voltage at the source in this configuration and adjust the divider until it is very roughly at about B+/2.
I tried and still the same, which is weird because you'd think that it would give you 95 volts but I'm reading 35V. Take not that I didnt connect it to the gate itself but to R29

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Huh. At 35V the headroom should be very asymmetric, but not gated. Very peculiar. The offset should be in the magnitude of the gate threshold voltage, which is at 2-4V according to the datasheet. Is there a chance that you shot the gate with electrostatic discharge during soldering? They're very sensitive without the protection zener.

Does the circuit work as it should without the buffer?

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Post by Reachahighernoon »

stolen wrote: 21 Sep 2021, 08:32 Huh. At 35V the headroom should be very asymmetric, but not gated. Very peculiar. The offset should be in the magnitude of the gate threshold voltage, which is at 2-4V according to the datasheet. Is there a chance that you shot the gate with electrostatic discharge during soldering? They're very sensitive without the protection zener.

Does the circuit work as it should without the buffer?
I mean it is possible, but two mosfets in a row? Are they THAT sensitive?

I've tested the circuit with a Jfet buffer using 12V and 2N3819 and it works perfectly

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Post by stolen »

Oh right, sorry, forgot about this. Grasping at straws a little here to be honest. Are you sure D5 is in the right direction? Could you try shorting R31?

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stolen wrote: 21 Sep 2021, 10:20 Oh right, sorry, forgot about this. Grasping at straws a little here to be honest. Are you sure D5 is in the right direction? Could you try shorting R31?
I am not sure about D5 but most schematics use it in this orientation, I tried shorting R31 but that didnt help

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Post by Manfred »

The orientation of D5 is in order.
D5 limits the voltage between gate and source, that is its task.
The maximum voltage is e.g. for the IRF820 +/- 20V.
The drawing symbol for D5 is wrong, it should be replaced by the one for a Z-diode.

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Post by Manfred »

Another possibility would be to use a buffer with the LND150 D-MOS FET, which is used here in the send stage of the shown FX-loop,
I found this schematic in the Net and kept it in my archive.
lnd150 FX-Loop schematic.png

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Manfred wrote: 21 Sep 2021, 18:43 Another possibility would be to use a buffer with the LND150 D-MOS FET, which is used here in the send stage of the shown FX-loop,
I found this schematic in the Net and kept it in my archive.
lnd150 FX-Loop schematic.png
Why is the LND150 so common? I see it more than any other mosfet

I also ended up using a jfet buffer powered by the 12V for the heaters

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Post by Manfred »

Why is the LND150 so common? I see it more than any other mosfet

I also ended up using a jfet buffer powered by the 12V for the heaters
The following concerns the comparison with Power-MOSFETs.
5 -10 times smaller input capacity.
Smaller noise figure.
Much smaller forward conductance, thus more suitable for the source circuit.
Smaller case (TO92).
I see that you have decided to use the JFET circuit.

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