Hello !
- I am impressed by this schematic !
- If it is not too late, i would appreciate if Bajaman could email me the AES2004 paper of Dimitri (Hello !), to improve my knowledge !
- I made some Spice simulations & Proto of Jfet cascode, ActiveLoad etc.. but i never saw that (about Ao2 + Ao3 Loop around the JFet !).
In my understanding, to complete as Baracuda said, it is like a HiGain DCloop to "DC"Feedback the Jfet Drain at +Vcc/2: the output of the loop (via R=100) is a Voltage to Current source (seems Integrator+Rsense modified Howland) which feeds an +Vbias with "AC very lowZin" at the AOe-/DrainFet point, to cancel the Miller Effect, but mainly in order to Adjust the AC Gain of this stage (Jfet+Ao2) via 10K Trim Without changing the Ao2 Vout DC Idle @ +1/2Vcc: this ensure that the Ao will never "disturb" the wanted JFET non-linearity.
- Its some thoughts !
